The Art of Analog Layout. Alan Hastings

The Art of Analog Layout



Download The Art of Analog Layout



The Art of Analog Layout Alan Hastings ebook pdf
Publisher: Prentice Hall
Language: English
Page: 668
ISBN: 0131464108, 9780131464100

Verbal explanations are favored over mathematical formulas, graphs are kept to a minimum, and line drawings are used in this user-friendly book. Clear guidance and advice are provided for those professionals who lay out analog circuits. Matching of resistors and capacitors: Includes causes of mismatch, particularly the hydrogen effect and package shift. MOS Transistors: Covers a brief history of floating gate devices, EPROM and EEPROM. Applications of MOS transistors: Expands information on failure mechanisms, including BVdss/Bvdii, SILC, NBTI/PTBI and GIDL and the difference between electrical and electrothermal SOA. Consideration of failure mechanisms as crucial to layout: Integrates further information into many chapters covering various devices. Standard bipolar, polygate CMOS and analog BiCMOS: Covers all three fundamental processes. A valuable reference for professional layout designers.

From the Back Cover

Based on the author's extensive experience as a circuit designer and a layout designer, The Art of Analog Layout takes a practical and authoritative perspective, providing the reader with broad coverage of the issues involved in successfully laying out analog integrated circuits. Topics range from the mechanics of layout to essential information about many related areas, such as device physics, processing failure modes and effects, device operation, parasitics, and matching. The emphasis throughout is on practical knowledge.

Written for layout designers, the mathematics is kept to a minimum, requiring only a familiarity with basic algebra and elementary electronics. Provides a carrier-based model for understanding device operation. Focuses on three processes: standard bipolar, polysilicon-gate CMOS, and analog BICMOS, enabling the reader to comprehend most new processes. Discusses the ways in which variations in layout geometries affect the performance of devices fabricated in silicon. Many exercises can be completed using pencil and paper for those who do not have access to layout editing software.
--This text refers to an out of print or unavailable edition of this title.



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